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EffiTest2: Efficient Delay Test and Prediction for Post-Silicon Clock Skew Configuration Under Process Variations., , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (4): 705-718 (2019)PathDriver+: Enhanced Path-Driven Architecture Design for Flow-Based Microfluidic Biochips., , , , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (7): 2185-2198 (2022)Logic Design of Neural Networks for High-Throughput and Low-Power Applications., , , и . CoRR, (2023)Hardware-Software Codesign of Weight Reshaping and Systolic Array Multiplexing for Efficient CNNs., , , , и . DATE, стр. 667-672. IEEE, (2021)An Efficient Programming Framework for Memristor-based Neuromorphic Computing., , , , , , , , , и . DATE, стр. 1068-1073. IEEE, (2021)Robustness of Neuromorphic Computing with RRAM-based Crossbars and Optical Neural Networks., , , , , , , , , и . ASP-DAC, стр. 853-858. ACM, (2021)Machine Learning in Advanced IC Design: A Methodological Survey., , , , и . IEEE Des. Test, 40 (1): 17-33 (февраля 2023)Virtualsync: timing optimization by synchronizing logic waves with sequential and combinational components as delay units., , , и . DAC, стр. 26:1-26:6. ACM, (2018)Reliable and Robust RRAM-based Neuromorphic Computing., , , , , , , , и . ACM Great Lakes Symposium on VLSI, стр. 33-38. ACM, (2020)Application of machine learning methods in post-silicon yield improvement., , , , и . SoCC, стр. 243-248. IEEE, (2017)