Author of the publication

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Latch Clustering for Timing-Power Co-Optimization.

C. Huang, G. Téllez, G. Nam, and Y. Chang. DAC, page 1-6. IEEE, (2020)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Fong-Chin Huang

Chin-Rong Huang

Yen-Chin Huang

Stéphane Chau

Erika Chin

Other publications of authors with the same name

Detailed-Routing-Driven analytical standard-cell placement.C. Huang, C. Chiou, K. Tseng, and Y. Chang. ASP-DAC, page 378-383. IEEE, (2015)Latch Clustering for Timing-Power Co-Optimization.C. Huang, G. Téllez, G. Nam, and Y. Chang. DAC, page 1-6. IEEE, (2020)Clock-Aware Placement for Large-Scale Heterogeneous FPGAs.J. Chen, Z. Lin, Y. Kuo, C. Huang, Y. Chang, S. Chen, C. Chiang, and S. Kuo. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (12): 5042-5055 (2020)Routability-Driven Blockage-Aware Macro Placement.Y. Chen, C. Huang, C. Chiou, Y. Chang, and C. Wang. DAC, page 124:1-124:6. ACM, (2014)NTUplace4h: A Novel Routability-Driven Placement Algorithm for Hierarchical Mixed-Size Circuit Designs.M. Hsu, Y. Chen, C. Huang, S. Chou, T. Lin, T. Chen, and Y. Chang. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 33 (12): 1914-1927 (2014)Timing-driven cell placement optimization for early slack histogram compression.C. Huang, Y. Liu, Y. Lu, Y. Kuo, Y. Chang, and S. Kuo. DAC, page 81:1-81:6. ACM, (2016)Routability-driven placement for hierarchical mixed-size circuit designs.M. Hsu, Y. Chen, C. Huang, T. Chen, and Y. Chang. DAC, page 151:1-151:6. ACM, (2013)Clock-aware placement for large-scale heterogeneous FPGAs.Y. Kuo, C. Huang, S. Chen, C. Chiang, Y. Chang, and S. Kuo. ICCAD, page 519-526. IEEE, (2017)NTUplace4dr: A Detailed-Routing-Driven Placer for Mixed-Size Circuit Designs With Technology and Region Constraints.C. Huang, H. Lee, B. Lin, S. Yang, C. Chang, S. Chen, Y. Chang, T. Chen, and I. Bustany. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (3): 669-681 (2018)Graph-Based Logic Bit Slicing for Datapath-Aware Placement.C. Huang, B. Lin, H. Lee, Y. Chang, K. Wu, and J. Yang. DAC, page 71:1-71:6. ACM, (2017)

BibSonomy

Disambiguation of "Huang, Chau-Chin"

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Latch Clustering for Timing-Power Co-Optimization.

Please choose a person to relate this publication to

Fong-Chin Huang

Chin-Rong Huang

Yen-Chin Huang

Stéphane Chau

Erika Chin

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Huang, Chau-Chin"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Latch Clustering for Timing-Power Co-Optimization.

Please choose a person to relate this publication to

Fong-Chin Huang

Chin-Rong Huang

Yen-Chin Huang

Stéphane Chau

Erika Chin

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Latch Clustering for Timing-Power Co-Optimization.