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A current sensing completion detection method for asynchronous pipelines operating in the sub-threshold regime., , и . I. J. Circuit Theory and Applications, 37 (2): 203-220 (2009)High speed ASIC implementations of leakage-resilient cryptography., , , , , и . DATE, стр. 1259-1264. IEEE, (2018)A Modular and Scalable Architecture for the Realization of High-speed Programmable Rank Order Filters Using Threshold Logic., , и . VLSI Design, 11 (2): 115-128 (2000)Investigating the Potential of Custom Instruction Set Extensions for SHA-3 Candidates on a 16-bit Microcontroller Architecture., , и . IACR Cryptology ePrint Archive, (2012)A 2 Gb/s balanced AES crypto-chip implementation., , , , , , и . ACM Great Lakes Symposium on VLSI, стр. 39-44. ACM, (2004)Design and realization of a fault-tolerant 90nm CMOS cryptographic engine capable of performing under massive defect density., , , , и . ACM Great Lakes Symposium on VLSI, стр. 204-207. ACM, (2007)A 10-core SoC with 20 Fine-Grain Power Domains for Energy-Proportional Data-Parallel Processing over a Wide Voltage and Temperature Range., , , , , и . ESSCIRC, стр. 263-266. IEEE, (2021)The ECSEL FRACTAL Project: A Cognitive Fractal and Secure edge based on a unique Open-Safe-Reliable-Low Power Hardware Platform., , , , , , , , , и 1 other автор(ы). DSD, стр. 393-400. IEEE, (2020)PetaOps/W edge-AI $\mu$ Processors: Myth or reality?, , , , , , , , , и 18 other автор(ы). DATE, стр. 1-6. IEEE, (2023)Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs., , , , , , , , , и . ACM Trans. Reconfigurable Technol. Syst., 2 (2): 13:1-13:36 (2009)