Author of the publication

Characterization of 2-bit Recessed Channel Memory with Lifted-Charge Trapping Node (L-CTN) Scheme.

, , , , , , , , and . IEICE Trans. Electron., 91-C (5): 742-746 (2008)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Individual variation in 3D visual fatigue caused by stereoscopic images., and . IEEE Trans. Consumer Electronics, 58 (2): 500-504 (2012)An Intelligent Cache System with Hardware Prefetching for High Performance., , , and . IEEE Trans. Computers, 52 (5): 607-616 (2003)Libraries of hidden layer activity patterns can lead to better understanding of operating principles of deep neural networks.. CoRR, (2019)DynMat, a network that can learn after learning.. CoRR, (2018)Fog server deployment considering network topology and flow state in local area networks., , and . ICUFN, page 652-657. IEEE, (2017)Next High Performance and Low Power Flash Memory Package Structure.. J. Comput. Sci. Technol., 22 (4): 515-520 (2007)Multiuser Diversity for Secrecy Communications Using Opportunistic Jammer Selection: Secure DoF and Jammer Scaling Law., and . IEEE Trans. Signal Process., 62 (4): 828-839 (2014)A new cache architecture based on temporal and spatial locality., , and . J. Syst. Archit., 46 (15): 1451-1467 (2000)Temporal learning of bottom-up connections via spatially nonspecific top-down inputs., , and . Neurocomputing, (2020)Analyses on Current Characteristics of 3-D MOSFET Determined by Junction Doping Profiles for Nonvolatile Memory Devices., , , , , , , and . IEICE Trans. Electron., 90-C (5): 988-993 (2007)