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Disambiguation of "Kahng, Andrew B."

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The ITRS MPU and SOC system drivers: Calibration and implications for design-based equivalent scaling in the roadmap.

, , , and . ICCD, page 153-160. IEEE Computer Society, (2014)

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Andrew Stanka

Andrew Chester

Andrew MacFarlane

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Andrew Baker

 

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Wafer Topography-Aware Optical Proximity Correction., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (12): 2747-2756 (2006)Simultaneous Buffer Insertion and Wire Sizing Considering Systematic CMP Variation and Random Leff Variation., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 26 (5): 845-857 (2007)DAGSizer: A Directed Graph Convolutional Network Approach to Discrete Gate Sizing of VLSI Graphs., , , , and . ACM Trans. Design Autom. Electr. Syst., 28 (4): 52:1-52:31 (July 2023)Silicon Photonics for Computing Systems., , and . ACM J. Emerg. Technol. Comput. Syst., 14 (2): 20 (2018)Cross-Layer Co-Optimization of Network Design and Chiplet Placement in 2.5-D Systems., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (12): 5183-5196 (2020)In-Route Pin Access-Driven Placement Refinement for Improved Detailed Routing Convergence., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (3): 784-788 (2022)Hier-RTLMP: A Hierarchical Automatic Macro Placer for Large-scale Complex IP Blocks., , and . CoRR, (2023)A new methodology for reduced cost of resilience., , and . ACM Great Lakes Symposium on VLSI, page 157-162. ACM, (2014)Heuristic Methods for Fine-Grain Exploitation of FDSOI., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (10): 2860-2871 (2020)Optimal partitioners and end-case placers for standard-cell layout., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 19 (11): 1304-1313 (2000)