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A 2Mb ReRAM with two bits error correction codes circuit for high reliability application., , , , , , and . ASICON, page 1-4. IEEE, (2013)An Emerging NVM CIM Accelerator With Shared-Path Transpose Read and Bit-Interleaving Weight Storage for Efficient On-Chip Training in Edge Devices., , , , , , , , , and 2 other author(s). IEEE Trans. Circuits Syst. II Express Briefs, 70 (7): 2645-2649 (July 2023)HashC: Making deep learning coverage testing finer and faster., , , , and . J. Syst. Archit., (November 2023)A 9Mb HZO-Based Embedded FeRAM with 1012-Cycle Endurance and 5/7ns Read/Write using ECC-Assisted Data Refresh and Offset-Canceled Sense Amplifier., , , , , , , , , and 2 other author(s). ISSCC, page 498-499. IEEE, (2023)Novel 15T SRAM Cell for Low Voltage High Reliability Application., , , , , , , and . ASICON, page 1-4. IEEE, (2021)Nonvolatile Binary CNN Accelerator with Extremely Low Standby Power using RRAM for IoT Applications., , , , and . ASICON, page 1-4. IEEE, (2019)Novel RRAM programming technology for instant-on and high-security FPGAs., , , , , and . ASICON, page 291-294. IEEE, (2011)Dynamic Data-Dependent Reference to Improve Sense Margin and Speed of Magnetoresistive Random Access Memory., , , , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 64-II (2): 186-190 (2017)An Orthogonal Algorithm for Key Management in Hardware Obfuscation., , , , , , and . AsianHOST, page 1-4. IEEE, (2019)A 1T2R1C ReRAM CIM Accelerator With Energy-Efficient Voltage Division and Capacitive Coupling for CNN Acceleration in AI Edge Applications., , , , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 70 (1): 276-280 (2023)