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Prime+Abort: A Timer-Free High-Precision L3 Cache Attack using Intel TSX.

, , , and . USENIX Security Symposium, page 51-67. USENIX Association, (2017)

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Pentimento: Data Remanence in Cloud FPGAs., , , , , , and . ASPLOS (2), page 862-878. ACM, (2024)GoFetch: Breaking Constant-Time Cryptographic Implementations Using Data Memory-Dependent Prefetchers., , , , , , and . USENIX Security Symposium, USENIX Association, (2024)GPU.zip: On the Side-Channel Implications of Hardware-Based Graphical Data Compression., , , , , , and . SP, page 3716-3734. IEEE, (2024)Welcome to the Entropics: Boot-Time Entropy in Embedded Devices., , , , and . IEEE Symposium on Security and Privacy, page 589-603. IEEE Computer Society, (2013)Prime+Abort: A Timer-Free High-Precision L3 Cache Attack using Intel TSX., , , and . USENIX Security Symposium, page 51-67. USENIX Association, (2017)MAD: Microarchitectural Attacks and Defenses (Dagstuhl Seminar 23481)., , , and . Dagstuhl Reports, 13 (11): 151-166 (2023)Synchronization Storage Channels (S2C): Timer-less Cache Side-Channel Attacks on the Apple M1 via Hardware Synchronization Instructions., , , , and . USENIX Security Symposium, page 1973-1990. USENIX Association, (2023)Hertzbleed: Turning Power Side-Channel Attacks Into Remote Timing Attacks on x86., , , , , and . USENIX Security Symposium, page 679-697. USENIX Association, (2022)On Subnormal Floating Point and Abnormal Timing., , , , , and . IEEE Symposium on Security and Privacy, page 623-639. IEEE Computer Society, (2015)Avoiding Instruction-Centric Microarchitectural Timing Channels Via Binary-Code Transformations., , , , and . ASPLOS (2), page 120-136. ACM, (2024)