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End-to-End Optimization of Deep Learning Applications., , and . FPGA, page 133-139. ACM, (2020)A Millimeter-Wave CMOS Transceiver With Digitally Pre-Distorted PAM-4 Modulation for Contactless Communications., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 54 (6): 1600-1612 (2019)Overcoming Data Transfer Bottlenecks in DNN Accelerators via Layer-Conscious Memory Managment., , , , and . FPGA, page 120. ACM, (2019)Multilevel global placement with congestion control., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 22 (4): 395-409 (2003)Pseudopin assignment with crosstalk noise control., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 20 (5): 598-611 (2001)An efficient algorithm for performance-optimal FPGA technology mapping with retiming., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 17 (9): 738-748 (1998)DUNE-a multilayer gridless routing system., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 20 (5): 633-647 (2001)Over-the-cell channel routing., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 9 (4): 408-418 (1990)Optimality Study of Logic Synthesis for LUT-Based FPGAs., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 26 (2): 230-239 (2007)Protecting Combinational Logic Synthesis Solutions., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (12): 2687-2696 (2006)