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Disambiguation of "Zhang, Yaojun"

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Recent progresses of STT memory design and applications.

, , , , , and . ASICON, page 1-4. IEEE, (2015)

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Zhang Zhang

Meng Zhang

Methods and implementations of road-network matching. TU München, (2009)

Yan Zhang

Xianghong Zhang

Miao Zhang

 

Other publications of authors with the same name

Workspace analysis of a novel 6-dof cable-driven parallel robot., , , and . ROBIO, page 2403-2408. IEEE, (2009)A 1.041-Mb/mm2 27.38-TOPS/W Signed-INT8 Dynamic-Logic-Based ADC-less SRAM Compute-in-Memory Macro in 28nm with Reconfigurable Bitwise Operation for AI and Embedded Applications., , , , , , , , , and 2 other author(s). ISSCC, page 188-190. IEEE, (2022)Exploring the opportunity of implementing neuromorphic computing systems with spintronic devices., , , , , and . DATE, page 109-112. IEEE, (2018)Loadsa: A yield-driven top-down design method for STT-RAM array., , , and . ASP-DAC, page 291-296. IEEE, (2013)Exploration of GPGPU Register File Architecture Using Domain-wall-shift-write based Racetrack Memory., , , , and . DAC, page 196:1-196:6. ACM, (2014)ADAMS: asymmetric differential STT-RAM cell structure for reliable and high-performance applications., , , , and . ICCAD, page 9-16. IEEE, (2013)The analysis of resolution for cable-driven haptic device., , , and . ROBIO, page 715-719. IEEE, (2010)Giant Spin-Hall assisted STT-RAM and logic design., , , , , , and . Integr., (2017)On-chip caches built on multilevel spin-transfer torque RAM cells and its optimizations., , , , , and . ACM J. Emerg. Technol. Comput. Syst., 9 (2): 16:1-16:22 (2013)C1C: A configurable, compiler-guided STT-RAM L1 cache., , , , and . ACM Trans. Archit. Code Optim., 10 (4): 52:1-52:22 (2013)