( en | de | ru )

 

Disambiguation of "Llabería, José María"

Author of the publication

copydeleteadd this publication to your clipboard
MNEMOSENE++: Scalable Multi-Tile Design with Enhanced Buffering and VGSOT-MRAM based Compute-in-Memory Crossbar Array.

, , , , , , , , , , and . ICECS, page 1-5. IEEE, (2023)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

María José Benítez Romero

María José Carrascosa Gómez

María José Mendiburo Seguel

José María Navarro Adriaensens

José-Maria Hinz

 

Other publications of authors with the same name

Counteracting Bank Misprediction in Sliced First-Level Caches., , , and . Euro-Par, volume 2790 of Lecture Notes in Computer Science, page 586-596. Springer, (2003)Tradeoffs in Buffering Memory State for Thread-Level Speculation in Multiprocessors., , , , , and . HPCA, page 191-202. IEEE Computer Society, (2003)Increasing the Effective Bandwidth of Complex Memory Systems in Multivector Processors., and . SC, page 26. IEEE Computer Society, (1996)An Enhancement for a Scheduling Logic Pipelined over two Cycles ., , , and . ICCD, page 203-209. IEEE, (2006)Exploiting reuse locality on inclusive shared last-level caches., , , and . ACM Trans. Archit. Code Optim., 9 (4): 38:1-38:19 (2013)A Mechanism for Verifying Data Speculation., , and . Euro-Par, volume 3149 of Lecture Notes in Computer Science, page 525-534. Springer, (2004)A performance evaluation of the multiple bus network for multiprocessor systems., , , , and . SIGMETRICS, page 200-206. ACM, (1983)Performance evaluation of transputer systems with linear algebra problems., , , and . Microprocessing and Microprogramming, 32 (1-5): 825-832 (1991)Store Buffer Design for Multibanked Data Caches., , , and . IEEE Trans. Computers, 58 (10): 1307-1320 (2009)Tradeoffs in buffering speculative memory state for thread-level speculation in multiprocessors., , , , , and . ACM Trans. Archit. Code Optim., 2 (3): 247-279 (2005)