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Disambiguation of "Cheng, Yuanqing"

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ODESY: a novel 3T-3MTJ cell design with optimized area DEnsity, scalability and latencY.

, , , , and . ICCAD, page 118. ACM, (2016)

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Yuanqing Gao

Yuanqing Guo

Cheng-Yung Cheng

Ying Min Cheng

Yao Cheng

 

Other publications of authors with the same name

A Study of 3-D Power Delivery Networks With Multiple Clock Domains., and . IEEE Trans. Very Large Scale Integr. Syst., 24 (11): 3218-3231 (2016)NEAR: A Novel Energy Aware Replacement Policy for STT-MRAM LLCs., , , , and . ISCAS, page 1-5. IEEE, (2018)PSI Conscious Write Scheduling: Architectural Support for Reliable Power Delivery in 3-D Die-Stacked PCM., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (5): 1613-1625 (2016)STT-RAM Buffer Design for Precision-Tunable General-Purpose Neural Network Accelerator., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (4): 1285-1296 (2017)Power Supply Noise Aware Task Scheduling on Homogeneous 3D MPSoCs Considering the Thermal Constraint., , , , and . J. Comput. Sci. Technol., 33 (5): 966-983 (2018)A body-biasing of readout circuit for STT-RAM with improved thermal reliability., , , , , and . ISCAS, page 1530-1533. IEEE, (2015)SIP: Boosting Up Graph Computing by Separating the Irregular Property Data., , and . ACM Great Lakes Symposium on VLSI, page 15-20. ACM, (2020)Channel Modeling and Reliability Enhancement Design Techniques for STT-MRAM., , , , , , and . ISVLSI, page 461-466. IEEE Computer Society, (2015)An efficient all-digital IR-Drop Alarmer for DVFS-based SoC., , , , , , , , , and . ISCAS, page 221-224. IEEE, (2016)A case of precision-tunable STT-RAM memory design for approximate neural network., , , , , and . ISCAS, page 1534-1537. IEEE, (2015)