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Shift-based Primitives for Efficient Convolutional Neural Networks., , , and . CoRR, (2018)Novel and efficient min cut based voltage assignment in gate level., , , , , and . ISQED, page 150-155. IEEE, (2011)Floorplanning with Abutment Constraints and L-Shaped/T-Shaped Blocks based on Corner Block List., , , , , and . DAC, page 770-775. ACM, (2001)An integrated floorplanning with an efficient buffer planning algorithm., , , , , , and . ISPD, page 136-142. ACM, (2003)Rethinking thermal via planning with timing-power-temperature dependence for 3D ICs., , , , , and . ASP-DAC, page 261-266. IEEE, (2011)VLSI floorplanning with boundary constraints based on corner block list., , , , , and . ASP-DAC, page 509-514. ACM, (2001)LP based white space redistribution for thermal via planning and performance optimization in 3D ICs., , , , and . ASP-DAC, page 209-212. IEEE, (2008)Automatic enhanced CDFG generation based on runtime instrumentation., , , and . CSCWD, page 92-97. IEEE, (2013)Variation-Aware Supply Voltage Assignment for Simultaneous Power and Aging Optimization., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 20 (11): 2143-2147 (2012)Thermal-aware P/G TSV planning for IR drop reduction in 3D ICs., , , , , and . Integr., 46 (1): 1-9 (2013)