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Checking signal transition graph implementability by symbolic BDD traversal.

, , , , , и . ED&TC, стр. 325-332. IEEE Computer Society, (1995)

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Sergey Yakovlev

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Alexandre Alexeev

 

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Signal Graphs: From Self-Timed to Timed Ones., и . PNPM, стр. 199-206. IEEE Computer Society, (1985)Methodology and Tools for State Encoding in Asynchronous Circuit Synthesis., , , , и . DAC, стр. 63-66. ACM Press, (1996)Analyzing Semantics of Concurrent Hardware Specifications., и . ICPP (3), стр. 211-218. Pennsylvania State University Press, (1989)0-271-00686-2.Synthesis of Speed-Independent Circuits from STG-Unfolding Segment., , , , и . DAC, стр. 16-21. ACM Press, (1997)Global interconnections in FPGAs: modeling and performance analysis., , , , , и . SLIP, стр. 51-58. ACM, (2008)Low Latency Synchronization Through Speculation., и . PATMOS, том 3254 из Lecture Notes in Computer Science, стр. 278-288. Springer, (2004)Hardware and Petri Nets: Application to Asynchronous Circuit Design., , , , и . ICATPN, том 1825 из Lecture Notes in Computer Science, стр. 1-15. Springer, (2000)Editorial - Selected papers from the 16th IEEE International Symposium on Asynchronous Circuits and Systems., и . IET Comput. Digit. Tech., 5 (4): 316-317 (2011)WCET Analysis of Superscalar Processors Using Simulation With Coloured Petri Nets., , и . Real Time Syst., 18 (2/3): 275-288 (2000)Synthesis of Nets with Step Firing Policies., , , и . Fundam. Informaticae, 94 (3-4): 275-303 (2009)