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Disambiguation of "Ogawa, Junji"

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Split capacitor DAC mismatch calibration in successive approximation ADC.

, , , , , , , , , , , and . CICC, page 279-282. IEEE, (2009)

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Akio Ogawa

Junji Liu

Masahiro Ogawa

Junji Kato

Akira Ogawa

 

Other publications of authors with the same name

Split capacitor DAC mismatch calibration in successive approximation ADC., , , , , , , , , and 2 other author(s). CICC, page 279-282. IEEE, (2009)Circuits for CMOS High-Speed I/O in Sub-100 nm Technologies., , , , , , and . IEICE Trans. Electron., 89-C (3): 300-313 (2006)A 64Mbit Mesochronous Hybrid Wave Pipelined Multibank DRAM Macro., and . Intelligent Memory Systems, volume 2107 of Lecture Notes in Computer Science, page 1-14. Springer, (2000)A 40-to-44Gb/s 3�? Oversampling CMOS CDR/1: 16 DEMUX., , , , , , , , , and . ISSCC, page 224-598. IEEE, (2007)20-GHz Quadrature Injection-Locked LC Dividers With Enhanced Locking Range., , , , , and . IEEE J. Solid State Circuits, 43 (3): 610-618 (2008)18-GHz Clock Distribution Using a Coupled VCO Array., , , , , and . IEICE Trans. Electron., 90-C (4): 811-822 (2007)A 10-Gb/s receiver with series equalizer and on-chip ISI monitor in 0.11-μm CMOS., , , , , and . IEEE J. Solid State Circuits, 40 (4): 986-993 (2005)500-Mb/s nonprecharged data bus for high-speed DRAM's., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 33 (11): 1720-1730 (1998)A 0.8-1.3V 16-channel 2.5Gb/s high-speed serial transceiver in a 90nm standard CMOS process., , , , , , , , , and . CICC, page 131-134. IEEE, (2005)A Single-40 Gb/s Dual-20 Gb/s Serializer IC With SFI-5.2 Interface in 65 nm CMOS., , , , , , , , , and 8 other author(s). IEEE J. Solid State Circuits, 44 (12): 3580-3589 (2009)