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An efficient test vector compression technique based on block merging.. ISCAS, IEEE, (2006)A new collaborative scheme of test vector compression based on equal-run-length coding (ERLC)., and . CSCWD, page 21-25. IEEE, (2009)FPGA-Based Accelerators of Deep Learning Networks for Learning and Classification: A Review., , and . IEEE Access, (2019)Optimization of FPGA-based CNN Accelerators Using Metaheuristics., , , and . CoRR, (2022)A Geometric-Primitives-Based Compression Scheme for Testing Systems-on-a-Chip., , and . VTS, page 54-61. IEEE Computer Society, (2001)An Efficient Test Relaxation Technique for Combinational & Full-Scan Sequential Circuits., and . VTS, page 53-59. IEEE Computer Society, (2002)FxP-QNet: A Post-Training Quantizer for the Design of Mixed Low-Precision DNNs with Dynamic Fixed-Point Representation., , , and . CoRR, (2022)An efficient test relaxation technique for combinational circuits based on critical path tracing., and . ICECS, page 461-465. IEEE, (2002)Delay-fault testability preservation of the concurrent decomposition and factorization transformations., and . VTS, page 15-21. IEEE Computer Society, (1994)Using input/output queues to increase LDPC decoder performance., , and . AICCSA, page 304-308. IEEE Computer Society, (2008)