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From Interconnection Network To Task Level Analysis.

, , and . ICPP (1), page 73-77. Pennsylvania State University Press, (1989)

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Design and Performance of Generalized Interconnection Networks., and . IEEE Trans. Computers, 32 (12): 1081-1090 (1983)Performance Evaluation of a Dataflow Architecture., and . IEEE Trans. Computers, 39 (5): 615-627 (1990)Bandwidth Availability of Multiple-Bus Multiprocessors., and . IEEE Trans. Computers, 34 (10): 918-926 (1985)Fair Scheduling in Internet Routers., and . IEEE Trans. Computers, 51 (6): 686-701 (2002)Finite Buffer Analysis of Multistage Interconnection Networks., and . IEEE Trans. Computers, 43 (2): 243-247 (1994)VLSI Performance of Multistage Interconnection Network Using 4*4 Switches., and . ICDCS, page 606-613. IEEE Computer Society, (1982)Evaluating Virtual Channels for Cache-Coherent Shared-Memory Multiprocessors., and . International Conference on Supercomputing, page 253-260. ACM, (1996)A new IP lookup cache for high performance IP routers., , and . DAC, page 338-343. ACM, (2010)Performance characterization of multi-thread and multi-core processors based XML application oriented networking systems., , , and . J. Parallel Distributed Comput., 70 (5): 584-597 (2010)Efficient Mapping of Applications on Cache Based Multiprocessors., and . J. Parallel Distributed Comput., 19 (3): 179-191 (1993)