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A Unified code generation approach using mutation scheduling., , and . Code Generation for Embedded Processors, page 203-218. Kluwer, (1994)Novel Brain-Derived Algorithms Scale Linearly with Number of Processing Elements., , , , , , , and . PARCO, volume 15 of Advances in Parallel Computing, page 767-776. IOS Press, (2007)Data Partitioning Techniques for Partially Protected Caches to Reduce Soft Error Induced Failures., , , and . DIPES, volume 271 of IFIP, page 213-225. Springer, (2008)ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement, , , , and . CoRR, (2007)Generic Pipelined Processor Modeling and High Performance Cycle-Accurate Simulator Generation, and . CoRR, (2007)Guest Editorial: Special Issue on Self-Aware Systems on Chip., and . IEEE Des. Test, 35 (5): 5-6 (2018)Real-time analysis of resource-constrained distributed systems by simulation-guided model checking., and . SIGBED Rev., 5 (1): 7 (2008)HDGM: Hierarchical Dynamic Goal Management for Many-Core Resource Allocation., , and . IEEE Embed. Syst. Lett., 10 (3): 61-64 (2018)Fast Configurable-Cache Tuning With a Unified Second-Level Cache., , and . IEEE Trans. Very Large Scale Integr. Syst., 17 (1): 80-91 (2009)Biologically plausible models of homeostasis and STDP: Stability and learning in spiking neural networks., , , and . IJCNN, page 1-8. IEEE, (2013)