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Information Assurance Through Redundant Design: A Novel TNU Error-Resilient Latch for Harsh Radiation Environment., , , , , , , и . IEEE Trans. Computers, 69 (6): 789-799 (2020)Architecture of Cobweb-Based Redundant TSV for Clustered Faults., , , , , и . IEEE Trans. Very Large Scale Integr. Syst., 28 (7): 1736-1739 (2020)Design of a Novel Self-Recoverable SRAM Cell Protected Against Soft Errors., , , , , и . DSA, стр. 497-498. IEEE, (2019)Design of Double-Upset Recoverable and Transient-Pulse Filterable Latches for Low-Power and Low-Orbit Aerospace Applications., , , , , , , и . IEEE Trans. Aerosp. Electron. Syst., 56 (5): 3931-3940 (2020)A Soft-Error-Immune Quadruple-Node-Upset Tolerant Latch., , , , и . IEEE Trans. Aerosp. Electron. Syst., 59 (3): 2621-2632 (июня 2023)A Novel TDMA-Based Fault Tolerance Technique for the TSVs in 3D-ICs Using Honeycomb Topology., , , , , , , и . IEEE Trans. Emerg. Top. Comput., 9 (2): 724-734 (2021)Two Double-Node-Upset-Hardened Flip-Flop Designs for High-Performance Applications., , , , , , , и . IEEE Trans. Emerg. Top. Comput., 11 (4): 1070-1081 (октября 2023)Novel Low Cost, Double-and-Triple-Node-Upset-Tolerant Latch Designs for Nano-scale CMOS., , , , , , , и . IEEE Trans. Emerg. Top. Comput., 9 (1): 520-533 (2021)Novel Quadruple-Node-Upset-Tolerant Latch Designs With Optimized Overhead for Reliable Computing in Harsh Radiation Environments., , , , , , , , и . IEEE Trans. Emerg. Top. Comput., 10 (1): 404-413 (2022)Pattern Reorder for Test Cost Reduction Through Improved SVMRANK Algorithm., , , , , , и . IEEE Access, (2020)