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Power and area reduction in multi-stage addition using operand segmentation., , , and . VLSI-DAT, page 1-4. IEEE, (2013)Design of a Bone-Guided Cochlear Implant Microsystem With Monopolar Biphasic Multiple Stimulations and Evoked Compound Action Potential Acquisition and Its In Vivo Verification., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 56 (10): 3062-3076 (2021)A 2.17-mW Acoustic DSP Processor With CNN-FFT Accelerators for Intelligent Hearing Assistive Devices., , and . IEEE J. Solid State Circuits, 55 (8): 2247-2258 (2020)A Systolic Array Based GTD Processor With a Parallel Algorithm., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 62-I (4): 1099-1108 (2015)A 12.6 mW, 573-2901 kS/s Reconfigurable Processor for Reconstruction of Compressively Sensed Physiological Signals., , , and . IEEE J. Solid State Circuits, 54 (10): 2907-2916 (2019)A High-Throughput FPGA Accelerator for Short-Read Mapping of the Whole Human Genome., , , and . IEEE Trans. Parallel Distributed Syst., 32 (6): 1465-1478 (2021)An FM-Index Based High-Throughput Memory-Efficient FPGA Accelerator for Paired-End Short-Read Mapping., , , , , and . IEEE Trans. Biomed. Circuits Syst., 17 (6): 1331-1341 (December 2023)Iterative Receiver with a Lattice-Reduction-Aided MIMO Detector for IEEE 802.11ax., , , , , and . GLOBECOM, page 1-6. IEEE, (2020)Design optimization for ADMM-Based SVM Training Processor for Edge Computing., , and . AICAS, page 1-5. IEEE, (2021)24.5 A 0.5V 1.27mW nose-on-a-chip for rapid diagnosis of ventilator-associated pneumonia., , , , , , , , , and 9 other author(s). ISSCC, page 420-421. IEEE, (2014)