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Disambiguation of "Wei, Shaojun"

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SWPU: A 126.04 TFLOPS/W Edge-Device Sparse DNN Training Processor With Dynamic Sub-Structured Weight Pruning.

, , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 69 (10): 4014-4027 (2022)

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Shaojun Lu

Shaojun Tong

Wei Wei

Wei Wei

Wei Wei

 

Other publications of authors with the same name

Memory fartitioning-based modulo scheduling for high-level synthesis., , , , , and . ISCAS, page 1-4. IEEE, (2017)Reconfigurable computing - evolution of Von Neumann architecture.. FPT, IEEE, (2010)A 2.69 Mbps/mW 1.09 Mbps/kGE Conjugate Gradient-based MMSE Detector for 64-QAM 128×8 Massive MIMO Systems., , , , , and . A-SSCC, page 191-194. IEEE, (2018)LCP: a layer clusters paralleling mapping method for accelerating inception and residual networks on FPGA., , , , , and . DAC, page 16:1-16:6. ACM, (2018)An efficient kernel transformation architecture for binary- and ternary-weight neural network inference., , , , and . DAC, page 137:1-137:6. ACM, (2018)A Multi-Modal Face Recognition Method Using Complete Local Derivative Patterns and Depth Maps., , , , and . Sensors, 14 (10): 19561-19581 (2014)Data cache prefetching via context directed pattern matching for coarse-grained reconfigurable arrays., , , and . DAC, page 64:1-64:6. ACM, (2016)Polyhedral model based mapping optimization of loop nests for CGRAs., , , and . DAC, page 19:1-19:8. ACM, (2013)Aggressive Pipelining of Irregular Applications on Reconfigurable Hardware., , , , , and . ISCA, page 575-586. ACM, (2017)Energy-aware loops mapping on multi-vdd CGRAs without performance degradation., , , and . ASP-DAC, page 312-317. IEEE, (2017)