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Design approach for high-bandwidth low-power three-stage operational amplifiers.

, , , and . I. J. Circuit Theory and Applications, 40 (3): 263-273 (2012)

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Operating mode analysis of deep-submicron CMOS buffers driving inductive interconnects.. ICECS, page 491-494. IEEE, (2003)A new efficient SC integrator scheme for high-speed low-power applications., , and . I. J. Circuit Theory and Applications, 40 (8): 733-744 (2012)Corrections to "Settling Time Optimization for Three-Stage CMOS Amplifier Topologies" Dec 09 2569-2582., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 57-I (7): 1812-1813 (2010)Settling Time Optimization for Three-Stage CMOS Amplifier Topologies., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 56-I (12): 2569-2582 (2009)Special session: IEEE Real World Engineering Projects: Discovery-based curriculum modules for first-year students., , , , , , , , , and . FIE, page 1-2. IEEE Computer Society, (2012)Design approach for high-bandwidth low-power three-stage operational amplifiers., , , and . I. J. Circuit Theory and Applications, 40 (3): 263-273 (2012)Design of a 75-nW, 0.5-V subthreshold complementary metal-oxide-semiconductor operational amplifier., , , , and . I. J. Circuit Theory and Applications, 42 (9): 967-977 (2014)A Simple MOSFET Parasitic Capacitance Model and Its Application to Repeater Insertion Technique., , and . PATMOS, volume 4148 of Lecture Notes in Computer Science, page 311-318. Springer, (2006)Settling Time Minimization of Operational Amplifiers., , and . PATMOS, volume 4644 of Lecture Notes in Computer Science, page 107-116. Springer, (2007)A Time-Domain Model for Power Dissipation of CMOS Buffers Driving Lossy Transmission Lines., and . EUROMICRO, page 1204-1208. IEEE Computer Society, (1999)