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Disambiguation of "Amano, Hideharu"

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Cache Controller Design on Ultra Low Leakage Embedded Processors.

, , , , , , and . ARCS, volume 5455 of Lecture Notes in Computer Science, page 171-182. Springer, (2009)

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Hideharu Umehara

Kyoko Amano

Yu Amano

Shun'ichi Amano

 

Other publications of authors with the same name

A Preprocessing System of the EULASH: An Environment for Efficient use of Multiprocessors with Local Memory., , , , , and . Parallel and Distributed Computing and Systems, page 68-71. IASTED/ACTA Press, (1995)Total System Image of the Reconfigurable Machine WASMII., , , , and . PDPTA, page 1092-1096. CSREA Press, (1997)Performance Evaluation of 3-Dimensional MIN with Cache Consistency Maintenance Mechanism., , , , , and . PDPTA, page 1148-1154. CSREA Press, (2003)A Packet Forwarding Layer for DIMMnet and its Hardware Implementation., , , , , and . PDPTA, page 461-467. CSREA Press, (2005)Destination Bundle: A Routing Table Reduction Technique for Distributed Routing on Dependable Networks-on-Chips., , and . PDPTA, page 1343-1349. CSREA Press, (2005)A Routing Algorithm for DS-WDM Ring., , and . Applied Informatics, page 562-565. IASTED/ACTA Press, (1999)A prototype chip of multicontext FPGA with DRAM for virtual hardware., , and . ASP-DAC, page 17-18. ACM, (2001)An LSI implementation of the simple serial synchronized multistage interconnection network., , and . ASP-DAC, page 673-674. IEEE, (1997)Power reduction techniques for Dynamically Reconfigurable Processor Arrays., , , , , , , and . FPL, page 305-310. IEEE, (2008)Acceleration of ART Algorithm on an FPGA Board with Xilinx SDAccel., and . CANDAR Workshops, page 280-284. IEEE, (2019)