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Ultra-fast NoC emulation on a single FPGA., , and . FPL, page 1-8. IEEE, (2015)LEF: An Effective Routing Algorithm for Two-Dimensional Meshes., and . IEICE Trans. Inf. Syst., 102-D (10): 1925-1941 (2019)ProgressiveNN: Achieving Computational Scalability with Dynamic Bit-Precision Adjustment by MSB-first Accumulative Computation., , , , , , , and . Int. J. Netw. Comput., 11 (2): 338-353 (2021)Efficient COO to CSR Conversion for Accelerating Sparse Matrix Processing on FPGA., , , , and . ICCE, page 1-2. IEEE, (2024)Exploration of Hyperdimensional Computing Using Locality-Sensitive Hashing Mechanism on FPGA., , , , , and . ICCE, page 1-2. IEEE, (2024)High-Performance Hardware Merge Sorter., , and . FCCM, page 1-8. IEEE Computer Society, (2017)Pianissimo: A Sub-mW Class DNN Accelerator with Progressive Bit-by-Bit Datapath Architecture for Adaptive Inference at Edge., , , , , , , , , and . VLSI Technology and Circuits, page 1-2. IEEE, (2023)Dependency-Driven Trace-Based Network-on-Chip Emulation on FPGAs., , and . FPGA, page 211-221. ACM, (2020)ExtraFerns: Fully Parallel Ensemble Learning Technique with Random Projection and Non-Greedy yet Minimal Memory Access Training., , , , and . Int. J. Netw. Comput., 11 (2): 215-230 (2021)Pianissimo: A Sub-mW Class DNN Accelerator With Progressively Adjustable Bit-Precision., , , , , , , , , and . IEEE Access, (2024)