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A 5-GS/s 158.6-mW 9.4-ENOB Passive-Sampling Time-Interleaved Three-Stage Pipelined-SAR ADC With Analog-Digital Corrections in 28-nm CMOS.

, , , , , and . IEEE J. Solid State Circuits, 55 (6): 1553-1564 (2020)

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