( en | de | ru )

 

Disambiguation of "Papaefstathiou, Ioannis"

Author of the publication

copydeleteadd this publication to your clipboard
PRO3: A Hybrid NPU Architecture.

, , , , , , , , and . IEEE Micro, 24 (5): 20-33 (2004)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Ioannis Filippis

Ioannis Tzamichas

Ioannis Gavriel

Ioannis Efthimiadis

Ioannis Vardoulakis

 

Other publications of authors with the same name

A review of lightweight block ciphers., , , and . J. Cryptogr. Eng., 8 (2): 141-184 (2018)A novel embedded system for vision tracking., , and . DATE, page 1-4. European Design and Automation Association, (2014)Queue Management in Network Processors, , , , , and . CoRR, (2007)A Memory-Efficient Reconfigurable Aho-Corasick FSM Implementation for Intrusion Detection Systems., , and . ICSAMOS, page 186-193. IEEE, (2007)A novel low-power embedded object recognition system working at multi-frames per second., , and . ACM Trans. Embed. Comput. Syst., 12 (1s): 33:1-33:20 (2013)HC-CART: A parallel system implementation of data mining classification and regression tree (CART) algorithm on a multi-FPGA system., , , and . ACM Trans. Archit. Code Optim., 9 (4): 47:1-47:25 (2013)An FPGA-based queue management system for high speed networking devices., , , and . Microprocess. Microsystems, 28 (5-6): 223-236 (2004)A novel highly flexible network multi-processor optimised for reconfigurable devices., , , and . AFRICON, page 1-6. IEEE, (2013)Novel Reconfigurable Hardware Systems for Tumor Growth Prediction., , , and . ACM Trans. Comput. Heal., 2 (4): 28:1-28:27 (2021)Packet Processing acceleration with a 3-stage programmable pipeline engine., , , , and . IEEE Commun. Lett., 8 (3): 183-185 (2004)