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Disambiguation of "Zha, Yue"

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MEG: A RISCV-Based System Simulation Infrastructure for Exploring Memory Optimization Using FPGAs and Hybrid Memory Cube.

, , , , , and . FCCM, page 145-153. IEEE, (2019)

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Fangxing Zha

Jianing Zha

Haidi Yue

Chaofang Yue

Jenny Yuen

 

Other publications of authors with the same name

An Alternative Analytical Approach to Associative Processing., , and . IEEE Comput. Archit. Lett., 17 (2): 113-116 (2018)CMA: A Reconfigurable Complex Matching Accelerator for Wire-Speed Network Intrusion Detection., and . IEEE Comput. Archit. Lett., 17 (1): 33-36 (2018)Liquid Silicon: A Nonvolatile Fully Programmable Processing-in-Memory Processor With Monolithically Integrated ReRAM., , and . IEEE J. Solid State Circuits, 55 (4): 908-919 (2020)Liquid Silicon-Monona: A Reconfigurable Memory-Oriented Computing Fabric with Scalable Multi-Context Support., and . ASPLOS, page 214-228. ACM, (2018)When application-specific ISA meets FPGAs: a multi-layer virtualization framework for heterogeneous cloud FPGAs., and . ASPLOS, page 123-134. ACM, (2021)Challenges and Opportunities: From Near-memory Computing to In-memory Computing., , , and . ISPD, page 43-46. ACM, (2017)IMEC: A Fully Morphable In-Memory Computing Fabric Enabled by Resistive Crossbar., and . IEEE Comput. Archit. Lett., 16 (2): 123-126 (2017)Liquid Silicon: A Nonvolatile Fully Programmable Processing-In-Memory Processor with Monolithically Integrated ReRAM for Big Data/Machine Learning Applications., , and . VLSI Circuits, page 206-. IEEE, (2019)Virtualizing FPGAs in the Cloud., and . ASPLOS, page 845-858. ACM, (2020)ASPLOS 2020 was canceled because of COVID-19..Hyper-Ap: Enhancing Associative Processing Through A Full-Stack Optimization., and . ISCA, page 846-859. IEEE, (2020)