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Reconciling fault-tolerant distributed computing and systems-on-chip., and . Distributed Comput., 24 (6): 323-355 (2012)Brief announcement: how to speed-up fault-tolerant clock generation in VLSI systems-on-chip via pipelining., , and . PODC, page 276-277. ACM, (2009)Fast All-Digital Clock Frequency Adaptation Circuit for Voltage Droop Tolerance., , , and . ASYNC, page 68-77. IEEE Computer Society, (2018)How to Speed-Up Fault-Tolerant Clock Generation in VLSI Systems-on-Chip via Pipelining., , and . EDCC, page 230-239. IEEE Computer Society, (2010)The Involution Tool for Accurate Digital Timingand Power Analysis., , , and . PATMOS, page 1-8. IEEE, (2019)A Hybrid Delay Model for Interconnected Multi-Input Gates., , , and . CoRR, (2024)Reaching Agreement in Competitive Microbial Systems., , , , , , and . CoRR, (2021)A faithful binary circuit model with adversarial noise., , , , and . DATE, page 1327-1332. IEEE, (2018)Synthesis in presence of dynamic links., , , , and . Inf. Comput., 289 (Part): 104856 (2022)Distributed Computation with Continual Population Growth., , , , , and . DISC, volume 179 of LIPIcs, page 7:1-7:17. Schloss Dagstuhl - Leibniz-Zentrum für Informatik, (2020)