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A feature-rich NoC switch with cross-feature optimizations for the next generation of reliable and reconfigurable embedded systems.

, , , and . INA-OCMC@HiPEAC, page 2:1-2:4. ACM, (2014)

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Self-Calibrating Source Synchronous Communication for Delay Variation Tolerant GALS Network-on-Chip Design., , , and . Int. J. Embed. Real Time Commun. Syst., 2 (4): 1-20 (2011)Optimizing built-in pseudo-random self-testing for network-on-chip switches., , and . INA-OCMC@HiPEAC, page 21-24. ACM, (2012)Design space exploration of a mesochronous link for cost-effective and flexible GALS NOCs., , , , and . DATE, page 679-684. IEEE Computer Society, (2010)Ultra-low latency NoC testing via pseudo-random test pattern compaction., , , , and . ISSoC, page 1-6. IEEE, (2012)A library of dual-clock FIFOs for cost-effective and flexible MPSoC design., , and . ICSAMOS, page 20-27. IEEE, (2010)OSR-Lite: Fast and deadlock-free NoC reconfiguration framework., , , , , and . ICSAMOS, page 86-95. IEEE, (2012)Optimising pseudo-random built-in self-testing of fully synchronous as well as multisynchronous networks-on-chip., , , and . IET Comput. Digit. Tech., (2013)Design and Validation of Network-on-Chip Architectures for the Next Generation of Multi-synchronous, Reliable, and Reconfigurable Embedded Systems.. University of Ferrara, Italy, (2013)A feature-rich NoC switch with cross-feature optimizations for the next generation of reliable and reconfigurable embedded systems., , , and . INA-OCMC@HiPEAC, page 2:1-2:4. ACM, (2014)Cooperative Built-in Self-Testing and Self-Diagnosis of NoC Bisynchronous Channels., , , and . MCSoC, page 159-166. IEEE Computer Society, (2012)