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Using Statistical and Symbolic Simulation for Microprocessor Performance Evaluation.

, , и . J. Instruction-Level Parallelism, (2002)

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Matthew Mellon

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Peter Matthew

 

Другие публикации лиц с тем же именем

Utilizing Reuse Information in Data Cache Management., , , , и . International Conference on Supercomputing, стр. 449-456. ACM, (1998)Strategies for Achieving Improved Processor Throughput., и . ISCA, стр. 362-369. ACM, (1991)Dynamic Base Register Caching: A Technique for Reducing Address Bus Width., и . ISCA, стр. 128-137. ACM, (1991)A Study of Single-Chip Processor/Cache Organizations for Large Numbers of Transistors., , и . ISCA, стр. 338-347. IEEE Computer Society, (1994)Improving Execution Time of Parallel Programs on Large Scale Chip Multiprocessors with Constant Average Power Processing., , , , и . ICCD, стр. 649-652. IEEE Computer Society, (2017)Improving Provisioned Power Efficiency in HPC Systems with GPU-CAPP., , , , и . HiPC, стр. 112-122. IEEE, (2018)Techniques for extracting instruction level parallelism on MIMD architectures., и . MICRO, стр. 128-137. ACM / IEEE Computer Society, (1993)A modified approach to data cache management., , , и . MICRO, стр. 93-103. ACM / IEEE Computer Society, (1995)MISC: a Multiple Instruction Stream Computer., , и . MICRO, стр. 193-196. ACM / IEEE Computer Society, (1992)Analysis of the effect of core affinity on high-throughput flows., , , , , , и . NDM@SC, стр. 9-15. IEEE, (2014)