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Disambiguation of "Chui, Chi On"

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An Evaluation Framework for Nanotransfer Printing-Based Feature-Level Heterogeneous Integration in VLSI Circuits.

, , , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (5): 1858-1870 (2016)

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m-hwan ChuÌ

Yim-Pan Chui

Giwon On

Fabio Chui Pressinotti

Chui-jing Dcheng

 

Other publications of authors with the same name

Validating cascading of crossbar circuits with an integrated device-circuit exploration., , , and . NANOARCH, page 37-42. IEEE Computer Society, (2009)Synthesized Compact Models and Experimental Verifications for Substrate Noise Coupling in Mixed-Signal ICs., , , , , and . IEEE J. Solid State Circuits, 41 (8): 1817-1829 (2006)Nanoscale Application Specific Integrated Circuits., , , , , , , , , and . NANOARCH, page 99-106. IEEE Computer Society, (2011)Parameter Variability in Nanoscale Fabrics: Bottom-Up Integrated Exploration., , , , , , and . DFT, page 24-31. IEEE Computer Society, (2010)PROCEED: A pareto optimization-based circuit-level evaluator for emerging devices., , , and . ASP-DAC, page 818-824. IEEE, (2014)Synthesized compact model and experimental results for substrate noise coupling in lightly doped processes., , , , , and . CICC, page 469-472. IEEE, (2005)PROCEED: A Pareto Optimization-Based Circuit-Level Evaluator for Emerging Devices., , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (1): 192-205 (2016)Nanowire field-programmable computing platform., , , , , , and . NANOARCH, page 23-25. IEEE Computer Society, (2013)Variability in Nanoscale Fabrics: Bottom-up Integrated Analysis and Mitigation., , , , , , and . JETC, 9 (1): 8:1-8:24 (2013)An Evaluation Framework for Nanotransfer Printing-Based Feature-Level Heterogeneous Integration in VLSI Circuits., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (5): 1858-1870 (2016)