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A mechanism for reducing the cost of branches in RISC architectures.

, , and . Microprocess. Microprogramming, 24 (1-5): 565-572 (1988)

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Eliminating Cache Conflict Misses through XOR-Based Placement Functions., , , and . International Conference on Supercomputing, page 76-83. ACM, (1997)Improving Latency Tolerance of Multithreading through Decoupling., and . IEEE Trans. Computers, 50 (10): 1084-1094 (2001)Confidence Estimation for Branch Prediction Reversal., , , and . HiPC, volume 2228 of Lecture Notes in Computer Science, page 214-223. Springer, (2001)Vectorizing for Wider Vector Units in a HW/SW Co-designed Environment., , and . HPCC/EUC, page 518-525. IEEE, (2013)CROB: Implementing a Large Instruction Window through Compression., , , , and . Trans. High Perform. Embed. Archit. Compil., (2011)Chairmen's introduction., , and . Microprocess. Microprogramming, (1993)AGAMOS: A Graph-Based Approach to Modulo Scheduling for Clustered Microarchitectures., , , , and . IEEE Trans. Computers, 58 (6): 770-783 (2009)Hardware support for early register release., , , and . IJHPCN, 3 (2/3): 83-94 (2005)Reducing Branch Delay to Zero in Pipelined Processors., and . IEEE Trans. Computers, 42 (3): 363-371 (1993)Scalability of Broadcast Performance in Wireless Network-on-Chip., , , , , , and . IEEE Trans. Parallel Distributed Syst., 27 (12): 3631-3645 (2016)