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Buffer Size Reduction through Control-Flow Decomposition.

, , , и . RTCSA, стр. 183-190. IEEE Computer Society, (2007)

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Wassim Amine

Abu Bakr Ahmed Amine Nassr

Amine Ahriche

Amine Chaieb

Amine Bouabdallah

 

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AMICAL: Architectural Synthesis based on VHDL., , и . Synthesis for Control Dominated Circuits, том A-22 из IFIP Transactions, стр. 219-234. North-Holland, (1992)Scheduling with accurate communication delay model and scheduler implementation for multiprocessor system-on-chip., , , , и . Des. Autom. Embed. Syst., 11 (2-3): 167-191 (2007)Interactive System-level Partitioning with PARTIF., , и . EDAC-ETC-EUROASIC, стр. 464-468. IEEE Computer Society, (1994)Using abstract CPU subsystem simulation model for high level HW/SW architecture exploration., , , , и . ASP-DAC, стр. 969-972. ACM Press, (2005)A Loop-Based Scheduling Algorithm for Hardware Description Languages., , и . Parallel Process. Lett., (1994)System-on-a-Chip Cosimulation and Compilation., , , , и . IEEE Des. Test Comput., 14 (2): 16-25 (1997)A Scalable and Adaptable ILP-Based Approach for Task Mapping on MPSoC Considering Load Balance and Communication Optimization., , , , , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (9): 1744-1757 (2019)Communication Optimizations for Multithreaded Code Generation from Simulink Models., , , , , , , и . ACM Trans. Embed. Comput. Syst., 14 (3): 59:1-59:26 (2015)Hardware/software co-design of an ATM network interface card: a case study., , и . CODES, стр. 111-115. IEEE Computer Society, (1998)A unified model for co-simulation and co-synthesis of mixed hardware/software systems., , , , , и . ED&TC, стр. 180-184. IEEE Computer Society, (1995)