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A multi-story power delivery technique for 3D integrated circuits., , , и . ISLPED, стр. 57-62. ACM, (2008)A 2.1 pJ/bit, 8 Gb/s Ultra-Low Power In-Package Serial Link Featuring a Time-based Front-end and a Digital Equalizer., , , и . A-SSCC, стр. 187-190. IEEE, (2018)Leakage Power Analysis and Reduction for Nanoscale Circuits., , , , и . IEEE Micro, 26 (2): 68-80 (2006)A 0.4-1.6GHz spur-free bang-bang digital PLL in 65nm with a D-flip-flop based frequency subtractor circuit., , и . VLSIC, стр. 140-. IEEE, (2015)19.2 A 0.2-to-1.45GHz subsampling fractional-N all-digital MDLL with zero-offset aperture PD-based spur cancellation and in-situ timing mismatch detection., , и . ISSCC, стр. 326-327. IEEE, (2016)A fully integrated 40pF output capacitor beat-frequency-quantizer-based digital LDO with built-in adaptive sampling and active voltage positioning., , , , и . ISSCC, стр. 308-310. IEEE, (2018)A multi-phase VCO quantizer based adaptive digital LDO in 65nm CMOS technology., и . ISCAS, стр. 1-4. IEEE, (2017)Guest editors' introduction: Nanoscale Memories Pose Unique Challenges., и . IEEE Des. Test Comput., 28 (1): 6-8 (2011)Silicon Odometer: An On-Chip Reliability Monitor for Measuring Frequency Degradation of Digital Circuits., , и . IEEE J. Solid State Circuits, 43 (4): 874-880 (2008)Fault-tolerant ripple-carry binary adder using partial triple modular redundancy (PTMR)., , и . ISCAS, стр. 41-44. IEEE, (2015)