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Sibling-substitution-based BDD minimization using don't cares.

, , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 19 (1): 44-55 (2000)

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Linear cofactor relationships in Boolean functions., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (6): 1011-1023 (2006)Using simulation and satisfiability to compute flexibilities in Boolean networks., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (5): 743-755 (2006)Safe BDD Minimization Using Don't Cares., , , and . DAC, page 208-213. ACM Press, (1997)Overcoming Heterophobia: Modeling Concurrency in Heterogeneous Systems., , and . ACSD, page 13-. IEEE Computer Society, (2001)Modeling hierarchical combinational circuits., , , and . ICCAD, page 612-617. IEEE Computer Society / ACM, (1993)Refinement preserving approximations for the design and verification of heterogeneous systems., , and . Formal Methods Syst. Des., 31 (1): 1-33 (2007)Fair Mutual Exclusion with Unfair P and V Operations., and . Inf. Process. Lett., 21 (2): 97-100 (1985)Techniques for Verifying Superscalar Microprocessors.. DAC, page 552-557. ACM Press, (1996)Representing Circuits More Efficiently in Symbolic Model Checking., , and . DAC, page 403-407. ACM, (1991)Combining CTL, Trace Theory and Timing Models.. Automatic Verification Methods for Finite State Systems, volume 407 of Lecture Notes in Computer Science, page 334-348. Springer, (1989)