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A Mixed-Signal RISC-V Signal Analysis SoC Generator With a 16-nm FinFET Instance., , , , , , , , , and 21 other author(s). IEEE J. Solid State Circuits, 54 (10): 2786-2801 (2019)Computational Support for Multiplicity in Hierarchical Electronics Design., , , , and . SCF, page 1:1-1:11. ACM, (2022)Hierarchical Computational Design of Board-Level Electronics., , , , and . SCF, page 27:1-27:2. ACM, (2022)Beyond Schematic Capture: Meaningful Abstractions for Better Electronics Design Tools., , , , , , and . CHI, page 283. ACM, (2019)A 1×2 MIMO Multi-Band CMOS Transceiver with an Integrated Front-End in 90nm CMOS for 802.11a/g/n WLAN Applications., , , , , , , , , and 10 other author(s). ISSCC, page 356-357. IEEE, (2008)Opportunities and Challenges for Circuit Board Level Hardware Description Languages., and . CoRR, (2020)Turning coders into makers: the promise of embedded design generation., , , , , and . SCF, page 4:1-4:10. ACM, (2017)Cyclist: Accelerating hardware development., , , , , and . ICCAD, page 1011-1018. IEEE, (2017)An in-situ temperature-sensing interface based on a SAR ADC in 45nm LP digital CMOS for the frequency-temperature compensation of crystal oscillators., , , , , and . ISSCC, page 316-317. IEEE, (2010)JITPCB., , , , and . IROS, page 2230-2236. IEEE, (2016)