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Automatic generation of loop scheduling for VLIW., , , и . PACT, стр. 306-309. IFIP Working Group on Algol / ACM, (1995)Novel SRAM bias control circuits for a low power L1 data cache., , , , и . NORCHIP, стр. 1-6. IEEE, (2012)Access to streams in multiprocessor systems., , и . PDP, стр. 310-316. IEEE, (1993)A performance evaluation of the multiple bus network for multiprocessor systems., , , , и . SIGMETRICS, стр. 200-206. ACM, (1983)Dynamic Tolerance Region Computing for Multimedia., , и . IEEE Trans. Computers, 61 (5): 650-665 (2012)Picos: A hardware runtime architecture support for OmpSs., , , , и . Future Gener. Comput. Syst., (2015)Software and Hardware Techniques to Optimize Register File Utilization in VLIW Architectures., , , и . Int. J. Parallel Program., 32 (6): 447-474 (2004)Hybrid Transactional Memory with Pessimistic Concurrency Control., , , , , , , и . Int. J. Parallel Program., 39 (3): 375-396 (2011)Thread Lock Section-Aware Scheduling on Asymmetric Single-ISA Multi-Core., , , , и . IEEE Comput. Archit. Lett., 14 (2): 160-163 (2015)Increasing Memory Bandwidth with Wide Buses: Compiler, Hardware and Performance Trade-Offs., , , и . International Conference on Supercomputing, стр. 12-19. ACM, (1997)