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A Fault Tolerant Parallelism Approach for Implementing High-Throughput Pipelined Advanced Encryption Standard.

, and . J. Circuits Syst. Comput., 25 (9): 1650113:1-1650113:14 (2016)

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A Fault Tolerant Parallelism Approach for Implementing High-Throughput Pipelined Advanced Encryption Standard., and . J. Circuits Syst. Comput., 25 (9): 1650113:1-1650113:14 (2016)Warm Up before Circuit De-obfuscation? An Exploration through Bounded-Model-Checkers., , , and . HOST, page 13-16. IEEE, (2022)Threats on Logic Locking: A Decade Later., , , and . ACM Great Lakes Symposium on VLSI, page 471-476. ACM, (2019)Metrics-to-Methods: Decisive Reverse Engineering Metrics for Resilient Logic Locking., , , and . ACM Great Lakes Symposium on VLSI, page 685-690. ACM, (2023)RANE: An Open-Source Formal De-obfuscation Attack for Reverse Engineering of Logic Encrypted Circuits., , , and . ACM Great Lakes Symposium on VLSI, page 221-228. ACM, (2021)Advancing Trustworthiness in System-in-Package: A Novel Root-of-Trust Hardware Security Module for Heterogeneous Integration., , , , , , , , , and . IEEE Access, (2024)ReTrustFSM: Toward RTL Hardware Obfuscation-A Hybrid FSM Approach., , , , , and . IEEE Access, (2023)HLock+: A Robust and Low-Overhead Logic Locking at the High-Level Language., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (7): 2149-2162 (July 2023)DFSSD: Deep Faults and Shallow State Duality, A Provably Strong Obfuscation Solution for Circuits with Restricted Access to Scan Chain., , , , , , and . VTS, page 1-6. IEEE, (2020)SAT-Hard Cyclic Logic Obfuscation for Protecting the IP in the Manufacturing Supply Chain., , , and . IEEE Trans. Very Large Scale Integr. Syst., 28 (4): 954-967 (2020)