Author of the publication

A Compact Sub-nW/kHz Relaxation Oscillator Using a Negative-Offset Comparator With Chopping and Piecewise Charge-Acceleration in 28-nm CMOS.

, , , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 71 (2): 515-525 (February 2024)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A Compact Sub-nW/kHz Relaxation Oscillator Using a Negative-Offset Comparator With Chopping and Piecewise Charge-Acceleration in 28-nm CMOS., , , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 71 (2): 515-525 (February 2024)A 4.2-to-5.6 GHz Transformer-Based PMOS-only Stacked-gm VCO in 28-nm CMOS., , , , , , , , , and 1 other author(s). ICTA, page 36-37. IEEE, (2022)A 0.2-V Energy-Harvesting BLE Transmitter With a Micropower Manager Achieving 25% System Efficiency at 0-dBm Output and 5.2-nW Sleep Power in 28-nm CMOS., , , , , and . IEEE J. Solid State Circuits, 54 (5): 1351-1362 (2019)Accurate Performance Evaluation of Jitter-Power FOM for Multiplying Delay-Locked Loop., , , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 69 (2): 495-505 (2022)A 600-μm² Ring-VCO-Based Hybrid PLL Using a 30-μW Charge-Sharing Integrator in 28-nm CMOS., , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 68 (9): 3108-3112 (2021)Sampling and Comparator Speed-Enhancement Techniques for Near-Threshold SAR ADCs., , , , , , , and . IEEE Open J. Circuits Syst., (2021)A 0.0056mm2 all-digital MDLL using edge re-extraction, dual-ring VCOs and a 0.3mW block-sharing frequency tracking loop achieving 292fsrms Jitter and -249dB FOM., , , and . ISSCC, page 118-120. IEEE, (2018)A 0.0056-mm2 -249-dB-FoM All-Digital MDLL Using a Block-Sharing Offset-Free Frequency-Tracking Loop and Dual Multiplexed-Ring VCOs., , , and . IEEE J. Solid State Circuits, 54 (1): 88-98 (2019)A 10.6-mW 26.4-GHz Dual-Loop Type-II Phase-Locked Loop Using Dynamic Frequency Detector and Phase Detector., , , , and . IEEE Access, (2020)On the DC-Settling Process of the Pierce Crystal Oscillator in Start-Up., , , , , , , , , and 4 other author(s). IEEE Trans. Circuits Syst. II Express Briefs, 70 (1): 26-30 (2023)