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Disambiguation of "Sin, Sai-Weng"

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A Time-Interleaved 2nd-Order ΔΣ Modulator Achieving 5-MHz Bandwidth and 86.1-dB SNDR Using Digital Feed-Forward Extrapolation.

, , , , and . IEEE J. Solid State Circuits, 56 (8): 2375-2387 (2021)

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Sai Li

Sai Zhang

Sai Zhang

Sai Qian

Sin Wong

 

Other publications of authors with the same name

A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC., , , , and . IEEE J. Solid State Circuits, 51 (2): 365-377 (2016)An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC., , , , , , and . IEEE J. Solid State Circuits, 47 (11): 2763-2772 (2012)A 3.07 mW 30 MHz-BW 73.2 dB-SNDR Time- Interleaved Noise-Shaping SAR ADC With Self-Coupling Second-Order Error-Feedforward., , , , , , and . IEEE J. Solid State Circuits, 58 (10): 2722-2732 (October 2023)Polyphase Decomposition for Tunable Band-Pass Sigma-Delta A/D Converters., , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 5 (4): 537-547 (2015)A Two-Phase Multi-Bit Incremental ADC With Variable Loop Order., , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 70 (8): 2724-2728 (August 2023)An FPGA-Based Self-Reconfigurable Arc Fault Detection System for Smart Meters., , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 69 (10): 4133-4137 (2022)A 470-nA Quiescent Current and 92.7%/94.7% Efficiency DCT/PWM Control Buck Converter With Seamless Mode Selection for IoT Application., , , , , , and . IEEE Trans. Circuits Syst., 67-I (11): 4085-4098 (2020)Limit Cycle Oscillation Reduction for Digital Low Dropout Regulators., , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 63-II (9): 903-907 (2016)A 10-MHz Bandwidth Two-Path Third-Order ΣΔ Modulator With Cross-Coupling Branches., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 65-II (10): 1410-1414 (2018)Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC With Partial $V_cm$ -Based Switching., , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (3): 1168-1172 (2017)