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A High-Throughput Neural Network Accelerator., , , , , , и . IEEE Micro, 35 (3): 24-32 (2015)Efficient Resource Management during Instruction Scheduling for the EPIC Architecture., , , , , и . IEEE PACT, стр. 36-45. IEEE Computer Society, (2003)A low-cost memory interface for high-throughput accelerators., , , , , и . CASES, стр. 11:1-11:10. ACM, (2014)SWAP: Parallelization through Algorithm Substitution., , , , , и . IEEE Micro, 32 (4): 54-67 (2012)An Overview of the Open Research Compiler., , , , , , , и . LCPC, том 3602 из Lecture Notes in Computer Science, стр. 17-31. Springer, (2004)Efficient Modeling of Itanium Architecture during Instruction Scheduling using Extended Finite State Automata., , , , , и . J. Instruction-Level Parallelism, (2004)Rethinking Memory Management in Modern Operating System: Horizontal, Vertical or Random?, , , , и . IEEE Trans. Computers, 65 (6): 1921-1935 (2016)BPM/BPM+: Software-based dynamic memory partitioning mechanisms for mitigating DRAM bank-/channel-level interferences in multicore systems., , , , , и . ACM Trans. Archit. Code Optim., 11 (1): 5:1-5:28 (2014)Iterative optimization for the data center., , , , и . ASPLOS, стр. 49-60. ACM, (2012)Going vertical in memory management: Handling multiplicity by multi-policy., , , , , и . ISCA, стр. 169-180. IEEE Computer Society, (2014)