Author of the publication

Design of High-Performance and Area-Efficient Decoder for 5G LDPC Codes.

, , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 68 (2): 879-891 (2021)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

An Efficient 4-D 8PSK TCM Decoder Architecture., , and . IEEE Trans. Very Large Scale Integr. Syst., 18 (5): 808-817 (2010)A Universal Approximation Method and Optimized Hardware Architectures for Arithmetic Functions Based on Stochastic Computing., , , , , , and . IEEE Access, (2020)Automatic Generation of Dynamic Inference Architecture for Deep Neural Networks., , , , and . SiPS, page 117-122. IEEE, (2021)Column-Weighted Probabilistic GDBF Decoder for Irregular LDPC Codes., , , and . ISVLSI, page 1-6. IEEE, (2023)An FPGA-Based Reconfigurable CNN Training Accelerator Using Decomposable Winograd., , , and . ISVLSI, page 1-6. IEEE, (2023)A Reconfigurable Accelerator for Generative Adversarial Network Training Based on FPGA., , , and . ISVLSI, page 144-149. IEEE, (2021)Accelerating NLP Tasks on FPGA with Compressed BERT and a Hardware-Oriented Early Exit Method., , , and . ISVLSI, page 410-413. IEEE, (2022)Segmented successive cancellation list polar decoding with joint BCH-CRC codes., , , , and . ACSSC, page 1509-1513. IEEE, (2017)Memory-reduced MAP decoding for double-binary convolutional Turbo code., , and . ISCAS, page 469-472. IEEE, (2010)Low complexity, high speed decoder architecture for quasi-cyclic LDPC codes., and . ISCAS (6), page 5786-5789. IEEE, (2005)