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Cross-Layer Optimization for Multilevel Cell STT-RAM Caches.

, , , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (6): 1807-1820 (2017)

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Distributed replay protocol for distributed uniprocessors., , , , , , and . ICS, page 3-14. ACM, (2012)Exploring Applications of STT-RAM in GPU Architectures., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 68 (1): 238-249 (2021)FACRA: Flexible-Core Architecture Chip Resource Abstractor., , , , , , and . PDCAT, page 440-447. IEEE Computer Society, (2010)CD-ECC: content-dependent error correction codes for combating asymmetric nonvolatile memory operation errors., , , , , and . ICCAD, page 1-8. IEEE, (2013)An efficient STT-RAM-based register file in GPU architectures., , , , and . ASP-DAC, page 490-495. IEEE, (2015)TEMP: thread batch enabled memory partitioning for GPU., , , , , , and . DAC, page 65:1-65:6. ACM, (2016)Heterogeneous systems with reconfigurable neuromorphic computing accelerators., , , , , , and . ISCAS, page 125-128. IEEE, (2016)Unleashing the potential of MLC STT-RAM caches., , , and . ICCAD, page 429-436. IEEE, (2013)Cross-Layer Optimization for Multilevel Cell STT-RAM Caches., , , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (6): 1807-1820 (2017)An Energy-Efficient GPGPU Register File Architecture Using Racetrack Memory., , , , and . IEEE Trans. Computers, 66 (9): 1478-1490 (2017)