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Analysis of Subthreshold Finfet Circuits for Ultra-Low Power Design., , и . SoCC, стр. 91-92. IEEE, (2006)On-chip bus thermal analysis and optimisation., , , , , и . IET Comput. Digit. Tech., 1 (5): 590-599 (2007)A 130.7-mm2 2-Layer 32-Gb ReRAM Memory Device in 24-nm Technology., , , , , , , , , и 26 other автор(ы). IEEE J. Solid State Circuits, 49 (1): 140-153 (2014)Variation-Aware Task and Communication Mapping for MPSoC Architecture., , , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 30 (2): 295-307 (2011)Design exploration of hybrid caches with disparate memory technologies., , , , , и . ACM Trans. Archit. Code Optim., 7 (3): 15:1-15:34 (2010)Test-access mechanism optimization for core-based three-dimensional SOCs., , , и . Microelectron. J., 41 (10): 601-615 (2010)Global Convergence of Adaptive Gradient Methods for An Over-parameterized Neural Network., , и . CoRR, (2019)Linear Convergence of Adaptive Stochastic Gradient Descent., , и . CoRR, (2019)DeepSpeed-VisualChat: Multi-Round Multi-Image Interleave Chat via Multi-Modal Causal Attention., , , , , , , , и . CoRR, (2023)DeepSpeed Data Efficiency: Improving Deep Learning Model Quality and Training Efficiency via Efficient Data Sampling and Routing., , , , и . CoRR, (2022)