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Disambiguation of "Yoshida, Noriyoshi"

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Pin assignment with global routing for VLSI building block layout.

, , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 15 (12): 1575-1583 (1996)

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Takuro Yoshida

Daisuke Yoshida

Shingo Yoshida

Kazuhiko Yoshida

Shin Yoshida

 

Other publications of authors with the same name

A new system partitioning method under performance and physical constraints for multi-chip modules., , , and . ASP-DAC, ACM, (1995)Design of hardware algorithms by recurrence relations., , and . Syst. Comput. Jpn., 16 (3): 10-18 (1985)NP-completeness of some type of p-center problem., , and . Discret. Appl. Math., 2 (4): 361-363 (1980)Visualized and modeless programming environment for form manipulation language., , , and . VL, page 99-104. IEEE Computer Society, (1989)A new global routing algorithm for over-the-cell routing in standard cell layouts., , and . EURO-DAC, page 116-121. IEEE Computer Society, (1993)Gate Array Placement Based on Mincut, Partitioning with Path Delay Constraints., , , , and . ISCAS, page 2059-2062. IEEE, (1993)A Verification Algorithm for Logic Circuits with Internal Variables., , , and . ISCAS, page 1920-1923. IEEE, (1995)A linear algorithm for the domination number of a series-parallel graph., , and . Discret. Appl. Math., 5 (3): 299-311 (1983)A Method of Synthesis and Decomposition of Autonomous Linear Sequential Circuits, and . Inf. Control., 23 (4): 382-392 (November 1973)Diagonal Examples for Design Space Exploration in an Educational Environment CITY-1., and . MSE, page 71-73. IEEE Computer Society, (1999)