Author of the publication

Near-Optimal Microprocessor and Accelerators Codesign with Latency and Throughput Constraints.

, , , , and . ACM Trans. Archit. Code Optim., 10 (2): 6:1-6:25 (2013)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Novel codebook generation algorithms for vector quantization image compression., , and . ICASSP, page 2661-2664. IEEE, (1998)A local wavelet transform implementation versus an optimal row-column algorithm for the 2D multilevel decomposition., , , , , , and . ICIP (3), page 330-333. IEEE, (2001)A novel high-speed counter with counting rate independent of the counter's length., , , and . ICECS, page 1164-1167. IEEE, (2003)Efficient implementation of the keyed-hash message authentication code (HMAC) using the SHA-1 hash function., , , and . ICECS, page 567-570. IEEE, (2004)Partitioning DSP applications to different granularity reconfigurable hardware., , and . ICECS, page 1-4. IEEE, (2005)Evaluation of design alternatives for the 2-D-discrete wavelet transform., , , , and . IEEE Trans. Circuits Syst. Video Techn., 11 (12): 1246-1262 (2001)Resource aware mapping on coarse grained reconfigurable arrays., , , and . Microprocess. Microsystems, 33 (2): 91-105 (2009)Speedups from extending embedded processors with a high-performance coarse-grained reconfigurable data-path., and . J. Syst. Archit., 54 (5): 479-490 (2008)Server side hashing core exceeding 3 Gbps of throughput., , , , and . Int. J. Secur. Networks, 2 (3/4): 228-238 (2007)Energy Minimization Under Area and Performance Constraints for Multimedia Applications Realized on Embedded Cores., , , and . VLSI Design, 14 (3): 273-286 (2002)