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Performance-driven mapping for CPLD architectures., , , и . FPGA, стр. 39-47. ACM, (2001)Debugging and verifying SoC designs through effective cross-layer hardware-software co-simulation., , , , , и . DAC, стр. 7:1-7:6. ACM, (2016)Resource and data optimization for hardware implementation of deep neural networks targeting FPGA-based edge devices., , , и . SLIP@DAC, стр. 1:1-1:8. ACM, (2018)Throughput-oriented kernel porting onto FPGAs., , , , и . DAC, стр. 11:1-11:10. ACM, (2013)C-Mine: Data Mining of Logic Common Cases for Low Power Synthesis of Better-Than-Worst-Case Designs., , и . DAC, стр. 205:1-205:6. ACM, (2014)Optimality study of resource binding with multi-Vdds., , , и . DAC, стр. 580-585. ACM, (2006)Algorithm/Accelerator Co-Design and Co-Search for Edge AI., , , и . IEEE Trans. Circuits Syst. II Express Briefs, 69 (7): 3064-3070 (2022)VecQ: Minimal Loss DNN Model Compression With Vectorized Weight Quantization., , , , , и . IEEE Trans. Computers, 70 (5): 696-710 (2021)ASAP: Accelerated Short-Read Alignment on Programmable Hardware., , , , , , и . IEEE Trans. Computers, 68 (3): 331-346 (2019)A Routing Approach to Reduce Glitches in Low Power FPGAs., , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 29 (2): 235-240 (2010)