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Network Interface Architecture for Scalable Message Queue Processing.

N. Tanabe, A. Ohta, P. Waskito, and H. Nakajo. ICPADS, page 268-275. IEEE Computer Society, (2009)

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Hironori Kumeno

Hironori Tokuno

Other publications of authors with the same name

Implementation and Evaluation of a Thread Library for Multithreaded Architecture.K. Sasada, M. Sato, S. Kawahara, N. Kato, M. Yamato, H. Nakajo, and M. Namiki. PDPTA, page 609-615. CSREA Press, (2003)Performance evaluation on low-latency communication mechanism of DIMMnet-2.A. Kitamura, Y. Miyabe, T. Miyashiro, N. Tanabe, H. Nakajo, and H. Amano. Parallel and Distributed Computing and Networks, page 57-62. IASTED/ACTA Press, (2007)A memory accelerator with gather functions for bandwidth-bound irregular applications.N. Tanabe, B. Nuttapon, H. Nakajo, Y. Ogawa, J. Kogou, M. Takata, and K. Joe. IA3@SC, page 35-42. ACM, (2011)Implementation and Evaluation of the Mechanisms for Low Latency Communication on DIMMnet-2.Y. Miyabe, A. Kitamura, Y. Hamada, T. Miyashiro, T. Izawa, N. Tanabe, H. Nakajo, and H. Amano. ISHPC, volume 4759 of Lecture Notes in Computer Science, page 211-218. Springer, (2005)Operation in Partitioned Circuits with Scalable Hardware Mechanism.Y. Katoh, H. Yoshiuchi, Y. Murata, and H. Nakajo. JCSSE, page 1-6. IEEE, (2018)A New Memory Module for Memory Intensive Applications.N. Tanabe, H. Nakajo, H. Hakozaki, M. Nakatake, Y. Dohi, and H. Amano. PARELEC, page 123-128. IEEE Computer Society, (2004)Overview of the JUMP-1, an MPP prototype for general-purpose parallel computations.K. Hiraki, H. Amano, M. Kuga, T. Sueyoshi, T. Kudoh, H. Nakashima, H. Nakajo, H. Matsuda, T. Matsumoto, and S. ichiro Mori. ISPAN, page 427-434. IEEE Computer Society, (1994)Network Interface Architecture for Scalable Message Queue Processing.N. Tanabe, A. Ohta, P. Waskito, and H. Nakajo. ICPADS, page 268-275. IEEE Computer Society, (2009)Implementation of DNN on a RISC-V Open Source Microprocessor for IoT devices.J. Cai, M. Takemoto, and H. Nakajo. GCCE, page 295-299. IEEE, (2018)A Deep Look into Logarithmic Quantization of Model Parameters in Neural Networks.J. Cai, M. Takemoto, and H. Nakajo. IAIT, page 6:1-6:8. ACM, (2018)

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Disambiguation of "Nakajo, Hironori"

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Network Interface Architecture for Scalable Message Queue Processing.

Please choose a person to relate this publication to

Hironori Kumeno

Hironori Tokuno

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Nakajo, Hironori"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Network Interface Architecture for Scalable Message Queue Processing.

Please choose a person to relate this publication to

Hironori Kumeno

Hironori Tokuno

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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Network Interface Architecture for Scalable Message Queue Processing.