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Gate-Level Exception Handling Design for Noise Reduction in High-Speed VLSI Circuits., and . VLSI Design, page 109-114. IEEE Computer Society, (2007)The solid-state drive technology, today and tomorrow., , and . ICDE, page 1520-1522. IEEE Computer Society, (2015)A 20nm 1.8V 8Gb PRAM with 40MB/s program bandwidth., , , , , , , , , and 20 other author(s). ISSCC, page 46-48. IEEE, (2012)Timing Failure Analysis of Commercial CPUs Under Operating Stress., and . DFT, page 245-253. IEEE Computer Society, (2006)