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Disambiguation of "Pozzoni, Massimo"

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A wideband mm-Wave CMOS receiver for Gb/s communications employing interstage coupled resonators.

, , , , , , , , and . ISSCC, page 220-221. IEEE, (2010)

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Massimo Viola

Massimo Tallarida

Massimo Malagó

Massimo Moser

Massimo Busin

 

Other publications of authors with the same name

A 64 Gb/s Low-Power Transceiver for Short-Reach PAM-4 Electrical Links in 28-nm FDSOI CMOS., , , , , , , , , and . IEEE J. Solid State Circuits, 54 (1): 6-17 (2019)A high-speed low-voltage phase detector for clock recovery from NRZ data., , , and . ISCAS (4), page 297-300. IEEE, (2004)A 13.1% tuning range 115GHz frequency generator based on an injection-locked frequency doubler in 65nm CMOS., , , and . ISSCC, page 422-423. IEEE, (2010)A 12Gb/s 39dB loss-recovery unclocked-DFE receiver with bi-dimensional equalization., , , , , , , , and . ISSCC, page 164-165. IEEE, (2010)A sliding IF receiver for mm-wave WLANs in 65nm CMOS., , , , , , and . CICC, page 669-672. IEEE, (2009)A Multi-Standard 1.5 to 10 Gb/s Latch-Based 3-Tap DFE Receiver With a SSC Tolerant CDR for Serial Backplane Communication., , , , , , , , , and . IEEE J. Solid State Circuits, 44 (4): 1306-1315 (2009)Injection-Locked CMOS Frequency Doublers for μ -Wave and mm-Wave Applications., , , and . IEEE J. Solid State Circuits, 45 (8): 1565-1574 (2010)A 4.9pJ/b 16-to-64Gb/s PAM-4 VSR transceiver in 28nm FDSOI CMOS., , , , , , , , , and 2 other author(s). ISSCC, page 112-114. IEEE, (2018)A 10Gb/s receiver with linear backplane equalization and mixer-based self-aligned CDR., , , , , , , and . CICC, page 559-562. IEEE, (2008)A wideband mm-Wave CMOS receiver for Gb/s communications employing interstage coupled resonators., , , , , , , , and . ISSCC, page 220-221. IEEE, (2010)