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Disambiguation of "Biagioni, Andrea"

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APEnet+: a 3D toroidal network enabling Petaflops scale Lattice QCD simulations on commodity clusters

, , , , , , , , , , , , , and . CoRR, (2010)

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Andrea Witzenrath

Risikofaktoren für abdominelle Komplikationen nach kardiopulmonalem Bypass. Uni Erlangen-Nürnberg, (2009)

Andrea Rottach

Analysis of the cell cycle dependent dynamics of Dnmt1 and Np95 in living cells. Uni München, (2009)

Andrea Hruby

Die MAPKKK Bck1p des Zellwand-Integritätssignalwegs in der Bäckerhefe Saccharomyces cerevisiae. Uni Münster, (2009)

Michaela Andrea Fingas

Resultate nach radikaler Prostatektomie bei Patienten mit einem Prostatakarzinom Gleason 7-10. Uni Marburg, (2009)

Andrea Kunzmann

 

Other publications of authors with the same name

Distributed simulation of polychronous and plastic spiking neural networks: strong and weak scaling of a representative mini-application benchmark executed on a small-scale commodity cluster., , , , , , , , , and . CoRR, (2013)ASIP acceleration for virtual-to-physical address translation on RDMA-enabled FPGA-based network interfaces., , , , , , , , , and 2 other author(s). Future Gener. Comput. Syst., (2015)Design and implementation of a modular, low latency, fault-aware, FPGA-based network interface., , , , , , , , , and . ReConFig, page 1-6. IEEE, (2013)Real-Time Cortical Simulations: Energy and Interconnect Scaling on Distributed Systems., , , , , , , , , and 4 other author(s). PDP, page 283-290. IEEE, (2019)Impact of exponential long range and Gaussian short range lateral connectivity on the distributed simulation of neural networks including up to 30 billion synapses., , , , , , , , , and . CoRR, (2015)The Distributed Network Processor: a novel off-chip and on-chip interconnection network architecture, , , , , , , , , and . CoRR, (2012)NaNet: a flexible and configurable low-latency NIC for real-time trigger systems based on GPUs., , , , , , , , , and 3 other author(s). CoRR, (2013)APEnet+: a 3D toroidal network enabling Petaflops scale Lattice QCD simulations on commodity clusters, , , , , , , , , and 4 other author(s). CoRR, (2010)Virtual-to-Physical address translation for an FPGA-based interconnect with host and GPU remote DMA capabilities., , , , , , , , , and . FPT, page 58-65. IEEE, (2013)The Brain on Low Power Architectures - Efficient Simulation of Cortical Slow Waves and Asynchronous States., , , , , , , , , and 3 other author(s). PARCO, volume 32 of Advances in Parallel Computing, page 760-769. IOS Press, (2017)